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data sheet ics83940dyi revision c may 19, 2016 1 ?2016 integrated device technology, inc. low skew, 1-to18 lvpecl-to-lvcmos/lvttl fanout buffer ics83940di general description the ics83940di is a low skew, 1-to-18 lvpecl- to-lvcmos/lvttl fanout buffer. the ics83940di has two selectable clock inputs. the pclk, npclk pair can accept lvpec l, cml, or sstl input levels. the lvcmos_clk can accept lvcm os or lvttl input levels. the low impedance lvcmos/lvttl outp uts are designed to drive 50 ? series or parallel terminated transmission lines. the ics83940di is characterized at full 3.3v and 2.5v or mixed 3.3v core, 2.5v output operating su pply modes. guaranteed output and part-to-part skew characteristics make the ics83940di ideal for those clock distribution applications demanding well defined performance and repeatability. block diagram features ? eighteen lvcmos/lvttl outputs ? selectable lvcmos_clk or lvpecl clock inputs ? pclk, npclk pair can accept the following differential input levels: lvpecl, cml, sstl ? lvcmos_clk supports the following input types: lvcmos or lvttl ? maximum output frequency: 250mhz ? output skew: 150ps (maximum) ? part-to-part skew: 750ps (maximum) ? operating supply modes: ? core/output 3.3v/3.3v 3.3v/2.5v 2.5v/2.5v ? -40c to 85c ambient operating temperature ? lead-free (rohs 6) packaging ? for functional replacement part for 83940dkilf use 87016i pin assignments 32 lead vfqfn 5mm x 5mm x 0.925mm package body k package top view 32-lead lqfp 7mm x 7mm x 1.4mm package body y package top view clk_sel pclk npclk lvcmos_clk 0 1 18 q0:q17 pulldown pulldown pulldown pullup/pulldown 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 gnd gnd lvcmos_clk clk_sel pclk npclk v dd v ddo q6 q7 q8 v dd q9 q10 q11 gnd q17 q16 q15 gnd q14 q13 q12 v ddo q1 q2 v ddo q3 q4 q5 gnd q0 ics83940di 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 q6 q7 q8 v dd q9 q10 q11 gnd gnd gnd lvcmos_clk clk_sel pclk npclk v dd v ddo gnd q5 q4 q3 v ddo q2 q1 q0 q17 q16 q14 q15 gnd q13 q12 v ddo ics83940di product discontinuation no tice - last time buy ex pires may 6, 2017 (83940dkilf)
ics83940dyi revision c may 19, 2016 2 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer pin descriptions and characteristics table 1. pin descriptions note: pullup and pulldown refers to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics number name type description 1, 2, 12, 17, 25 gnd power power supply ground. 3 lvcmos_clk input pulldown single-ended clock input. lvcmos/lvttl interface levels. 4 clk_sel input pulldown clock select input. when high , selects lvcmos_clk input. when low, selects pclk, npclk inputs. lvcmos / lvttl interface levels. 5 pclk input pulldown non- inverting differentia l lvpecl clock input. 6npclkinput pullup/ pulldown inverting differential lvpecl clock input. v dd /2 default when left floating. 7, 21 v dd power power supply pin. 8, 16, 29 v ddo power output supply pins. 9, 10, 11, 13, 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 q17, q16, q15, q14, q13, q12, q11, q10, q9, q8, q7, q6, q5, q4, q3, q2, q1, q0 output single-ended clock outputs. lvcmos/lvttl interface levels. symbol parameter test conditio ns minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k ? r pulldown input pulldown resistor 51 k ? c pd power dissipation capacitance (per output) 6pf r out output impedance 18 28 ?
ics83940dyi revision c may 19, 2016 3 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer function tables table 3a. clock select function table table 3b. clock input function table note 1: please refer to the application information section, wiring the differential input to accept single-ended levels. control input clock clk_sel pclk, npclk lvcmos_clk 0 selected de-selected 1 de-selected selected inputs outputs input to output mode polarity clk_sel lvcmos_clk pclk npclk q[0:17] 0?01lowdifferential to single-endednon-inverting 0?10highdifferential to single-endednon-inverting 0 ? 0 biased; note 1 low single-ended to single-ended non-inverting 0 ? 1 biased; note 1 high single-ended to single-ended non-inverting 0 ? biased; note 1 0 high single-e nded to single-ended inverting 0 ? biased; note 1 1 low single-ended to single-ended inverting 10??lowsingle-ended to single-endednon-inverting 11??highsingle-ended to single-endednon-inverting
ics83940dyi revision c may 19, 2016 4 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to th e device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating co nditions for extended periods may affect product reliability. dc electrical characteristics table 4a. dc characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode voltage is defined as v ih . table 4b. dc characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode voltage is defined as v ih . item rating supply voltage, v dd 3.6v inputs, v i -0.3v to v dd + 0.3v outputs, v o -0.3v to v ddo + 0.3v input current, i in 20ma storage temperature, t stg -65 ? c to 150 ? c symbol parameter test conditio ns minimum typical maximum units v ih input high voltage lvcmos_clk 2.4 v dd v v il input low voltage lvcmos_clk 0.8 v i in input current 200 a v oh output high voltage i oh = -20ma 2.4 v v ol output low voltage i ol = 20ma 0.5 v v pp peak-to-peak input voltage; note 1 pclk, npclk 500 1000 mv v cmr common mode input voltage; note 1, 2 pclk, npclk v dd ? 1.45 v dd ? 0.6 v i dd power supply current 25 ma symbol parameter test conditio ns minimum typical maximum units v ih input high voltage lvcmos_clk 2.4 v dd v v il input low voltage lvcmos_clk 0.8 v i in input current 200 a v oh output high voltage i oh = -20ma 1.8 v v ol output low voltage i ol = 20ma 0.5 v v pp peak-to-peak input voltage; note 1 pclk, npclk 300 1000 mv v cmr common mode input voltage; note 1, 2 pclk, npclk v dd ? 1.4 v dd ? 0.6 v i dd power supply current 25 ma
ics83940dyi revision c may 19, 2016 5 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer table 4c. dc characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode voltage is defined as v ih . symbol parameter test conditio ns minimum typical maximum units v ih input high voltage lvcmos_clk 2 v dd v v il input low voltage lvcmos_clk 0.8 v i in input current 200 a v oh output high voltage i oh = -12ma 1.8 v v ol output low voltage i ol = 12ma 0.5 v v pp peak-to-peak input voltage; note 1 pclk, npclk 300 1000 mv v cmr common mode input voltage; note 1, 2 pclk, npclk v dd ? 1.4 v dd ? 0.6 v i dd power supply current 25 ma
ics83940dyi revision c may 19, 2016 6 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer ac electrical characteristics table 5a. ac characteristics, v dd = v ddo = 3.3v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature range , which is established when th e device is mounted in a test socket with maintained transverse airflow great er than 500 lfpm. the device wil l meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at 200mhz unless noted otherwise. note 1: measured from the differential input crossing point to the output v ddo /2. note 2: measured from v dd /2 to v ddo /2. note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as skew between outputs on different devices ope rating at the same supply voltage , same temperature and with eq ual load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: this parameter is defined in accordance with jedec standard 65. note 6: defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load condit ions. using the same type of inputs on each dev ice, the outputs are measured at v ddo /2. symbol parameter test conditio ns minimum typical maximum units f max output frequency 250 mhz t plh propagation delay pclk, npclk; note 1, 5 ? ? 150mhz 1.6 3.0 ns lvcmos_clk; note 2, 5 ? ? 150mhz 1.8 3.0 ns propagation delay pclk, npclk; note 1, 5 ? > 150mhz 1.6 3.3 ns lvcmos_clk; note 2, 5 ? > 150mhz 1.8 3.2 ns t sk(o) output skew; note 3, 5 pclk, npclk measured on the rising edge @ v ddo /2 150 ps lvcmos_clk 150 ps t sk(pp) part-to-part skew; note 6 pclk, npclk ? ? 150mhz 1.4 ns lvcmos_clk ? ? 150mhz 1.2 ns part-to-part skew; note 6 pclk, npclk ? > 150mhz 1.7 ns lvcmos_clk ? > 150mhz 1.4 ns part-to-part skew; note 4, 5 pclk, npclk measured on the rising edge @ v ddo /2 850 ps lvcmos_clk 750 ps t r / t f output rise/fall time 0.5v to 2.4v 0.3 1.1 ns odc output duty cycle ? < 134mhz 45 50 55 % 134mhz ? ? ? 250mhz 40 50 60 %
ics83940dyi revision c may 19, 2016 7 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer table 5b. ac characteristics, v dd = 3.3v 5%, v ddo = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature range , which is established when th e device is mounted in a test socket with maintained transverse airflow great er than 500 lfpm. the device wil l meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at 200mhz unless noted otherwise. note 1: measured from the differential input crossing point to the output v ddo /2. note 2: measured from v dd /2 to v ddo /2. note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as skew between outputs on different devices ope rating at the same supply voltage , same temperature and with eq ual load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: this parameter is defined in accordance with jedec standard 65. note 6: defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load condit ions. using the same type of inputs on each dev ice, the outputs are measured at v ddo /2. symbol parameter test conditio ns minimum typical maximum units f max output frequency 250 mhz t plh propagation delay pclk, npclk; note 1, 5 ? ? 150mhz 1.7 3.2 ns lvcmos_clk; note 2, 5 ? ? 150mhz 1.7 3.0 ns propagation delay pclk, npclk; note 1, 5 ? > 150mhz 1.6 3.4 ns lvcmos_clk; note 2, 5 ? > 150mhz 1.8 3.3 ns t sk(o) output skew; note 3, 5 pclk, npclk measured on the rising edge @ v ddo /2 150 ps lvcmos_clk 150 ps t sk(pp) part-to-part skew; note 6 pclk, npclk ? ? 150mhz 1.5 ns lvcmos_clk ? ? 150mhz 1.3 ns part-to-part skew; note 6 pclk, npclk ? > 150mhz 1.8 ns lvcmos_clk ? > 150mhz 1.5 ns part-to-part skew; note 4, 5 pclk, npclk measured on the rising edge @ v ddo /2 850 ps lvcmos_clk 750 ps t r / t f output rise/fall time 0.5v to 1.8v 0.3 1.2 ns odc output duty cycle ? < 134mhz 45 50 55 %
ics83940dyi revision c may 19, 2016 8 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer table 5c. ac characteristics, v dd = v ddo = 2.5v 5%, t a = -40c to 85c note: electrical parameters are guaranteed over the specified am bient operating temperature range , which is established when th e device is mounted in a test socket with maintained transverse airflow great er than 500 lfpm. the device wil l meet specifications after th ermal equilibrium has been reached under these conditions. note: all parameters measured at 200mhz unless noted otherwise. note 1: measured from the differential input crossing point to the output v ddo /2. note 2: measured from v dd /2 to v ddo /2. note 3: defined as skew between outputs at the same supply voltage and with equal load conditions. measured at v ddo /2. note 4: defined as skew between outputs on different devices ope rating at the same supply voltage , same temperature and with eq ual load conditions. using the same type of inputs on each device, the outputs are measured at v ddo /2. note 5: this parameter is defined in accordance with jedec standard 65. note 6: defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load condit ions. using the same type of inputs on each dev ice, the outputs are measured at v ddo /2. symbol parameter test conditio ns minimum typical maximum units f max output frequency 200 mhz t plh propagation delay pclk, npclk; note 1, 5 ? ? 150mhz 1.2 3.8 ns lvcmos_clk; note 2, 5 ? ? 150mhz 1.5 3.2 ns propagation delay pclk, npclk; note 1, 5 ? > 150mhz 1.5 3.7 ns lvcmos_clk; note 2, 5 ? > 150mhz 2.0 3.6 ns t sk(o) output skew; note 3, 5 pclk, npclk measured on the rising edge @ v ddo /2 200 ps lvcmos_clk 200 ps t sk(pp) part-to-part skew; note 6 pclk, npclk ? ? 150mhz 2.6 ns lvcmos_clk ? ? 150mhz 1.7 ns part-to-part skew; note 6 pclk, npclk ? > 150mhz 2.2 ns lvcmos_clk ? > 150mhz 1.7 ns part-to-part skew; note 4, 5 pclk, npclk measured on the rising edge @ v ddo /2 1.2 ns lvcmos_clk 1.0 ns t r / t f output rise/fall time 0.5v to 1.8v 0.3 1.2 ns odc output duty cycle ? < 134mhz 45 55 %
ics83940dyi revision c may 19, 2016 9 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer parameter measureme nt information 3.3v core/3.3v lvcmos output load ac test circuit 3.3v core/2.5v lvcmos output load ac test circuit part-to-part skew 2.5v core/2.5v lvcmos output load ac test circuit differential input level output skew scope qx gnd v dd, 1.65v5% -1.65v5% v ddo scope qx gnd v dd -1.25v5% 1.25v5% 2.05v5% v ddo t sk(pp) v ddo 2 v ddo 2 part 1 part 2 qx qy scope qx gnd v dd, 1.25v5% -1.25v5% v ddo v dd gnd pclk npclk v cmr cross points v pp t sk(o) v ddo 2 v ddo 2 qx qy
ics83940dyi revision c may 19, 2016 10 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer parameter measurement in formation, continued 3.3v output rise/fall time propagation delay 2.5v output rise/fall time output duty cycle/pulse width/period 0.5v 2.4v 2.4v 0.5v t r t f q0:q17 npclk q0:q17 pclk tp lh v ddo 2 v dd 2 lvcmos_clk 0.5v 1.8v 1.8v 0.5v t r t f q0:q17 t period t pw t period odc = v ddo 2 x 100% t pw q0:q17
ics83940dyi revision c may 19, 2016 11 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer application information wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v dd /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v dd = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v dd are at the same voltage. this configuration re quires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differ ential input can handle full rail lvcmos signaling, it is reco mmended that the amplitude be reduced. the datasheet specifie s a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v dd + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. t hey can be utilized for debugging purposes. the datasheet specific ations are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a di fferential input to accept single-ended levels
ics83940dyi revision c may 19, 2016 12 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer lvpecl clock input interface the pclk /npclk accepts l vpecl, cml, sstl and other differential signals. both differential signals must meet the v pp and v cmr input requirements. figures 2a to 2e show interface examples for the pclk/npclk input driven by the most common driver types. the input interfaces suggested here are examples only. if the driver is from another vendor, use their termination recommendation. please consult with the vendor of t he driver component to confirm the driver termination requirements. figure 2a. pclk/npclk input driven by a cml driver figure 2c. pclk/npclk input driven by a 3.3v lvpecl driver figure 2e. pclk/npclk input driven by an sstl driver figure 2b. pclk/npclk input driven by a built-in pullup cml driver figure 2d. pclk/npclk input driven by a 3.3v lvpecl driver with ac couple pclk npclk lvpecl input cml 3.3v zo = 50 zo = 50 3.3v 3.3v r1 50 r2 50 r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 zo = 50 pclk npclk 3.3v 3.3v lvpecl lvpecl input pclk npclk lvpecl input sstl 2.5v zo = 60 zo = 60 2.5v 3.3v r1 120 r2 120 r3 120 r4 120 pclk npclk 3.3v lvpecl input 3.3v zo = 50 zo = 50 r1 100 cml built-in pullup
ics83940dyi revision c may 19, 2016 13 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorporated on the printed circuit board (pcb) wit hin the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 3. the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the out er edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from t he package to the board through a solder joint, thermal vias are nece ssary to effectively conduct from the surface of the pcb to the gro und plane(s). the land pattern must be connected to ground through thes e vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application specific and dependent upon the package power dissipation as well as electrical conductivity requirement s. thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended t hat the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid any solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recommendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance leadframe base package, amkor technology. figure 3. p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) recommendations for unused input and output pins inputs: pclk/npclk inputs for applications not requiring the use of the differential input, both pclk and npclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from pclk to ground. lvcmos_clk input for applications not requiring the use of a clock input, it can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from the lvcmos_clk input to ground. lvcmos control pins all control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. outputs: lvcmos outputs all unused lvcmos output can be left floating. there should be no trace attached. solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
ics83940dyi revision c may 19, 2016 14 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer reliability information table 6a. ? ja vs. air flow table for a 32 lead lqfp table 6b. ? ja vs. air flow table for a 32 lead vfqfn transistor count the transistor count for ics83940di is: 820 ? ja vs. air flow linear feet per minute 0200500 multi-layer pcb, jedec standard te st boards 47.9c/w 42.1c/w 39.4c/w ? ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard te st boards 40.2c/w 35.1c/w 31.5c/w
ics83940dyi revision c may 19, 2016 15 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer package outline and package dimensions package outline - y suffix for 32 lead lqfp table 7a. package dimensions for 32 lead lqfp reference document: jedec publication 95, ms-026 jedec variation: abc - hd all dimensions in millimeters symbol minimum nominal maximum n 32 a 1.60 a1 0.05 0.10 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 0.20 d & e 9.00 basic d1 & e1 7.00 basic d2 & e2 5.60 ref. e 0.80 basic l 0.45 0.60 0.75 ? 0 7 ccc 0.10
ics83940dyi revision c may 19, 2016 16 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer package outline and package dimensions package outline - k suffix for 32 lead vfqfn table 7b. package dimensions reference document: jedec publication 95, mo-220 note: the following package mechanical drawing is a generic drawing that applies to any pin c ount vfqfn package. this drawing is not intended to convey the actual pin count or pin layout of this device. the pin count and pinout are shown on the front page. the package dimensions are in table 7b. to p view index area d cham fer 4x 0.6 x 0.6 max optional anvil singula tion a 0. 0 8 c c a3 a1 s eating plan e e2 e2 2 l (n -1)x e (r ef.) (ref.) n & n even n e d2 2 d2 (ref.) n & n odd 1 2 e 2 (ty p.) if n & n are even (n -1)x e (re f.) b th er mal ba se n or anvil s ing u l a tion n-1 n chamfer 1 2 n-1 1 2 n radius 4 4 bottom view w/type c id bottom view w/type a id there a re 2 method s of indic a ting pin 1 corner a t the ba ck of the vfqfn p a ck a ge: 1. type a: ch a mfer on the p a ddle (ne a r pin 1) 2. type c: mo us e b ite on the p a ddle (ne a r pin 1) jedec variation: vhhd-2/-4 all dimensions in millimeters symbol minimum nominal maximum n 32 a 0.80 1.00 a1 00.05 a3 0.25 ref. b 0.18 0.25 0.30 n d & n e 8 d & e 5.00 basic d2 & e2 3.0 3.3 e 0.50 basic l 0.30 0.40 0.50
ics83940dyi revision c may 19, 2016 17 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer ordering information table 8. ordering information part/order number marking packag e shipping packaging temperature 83940dyilf ics83940dyil ?lead-f ree? 32 lead lqfp tray -40 ? c to 85 ? c 83940dyilft ics83940dyil ?lead-free? 32 lead lqfp tape & reel -40 ? c to 85 ? c 83940dkilf ics83940dil ?lead-free? 32 lead vfqfn tray -40 ? c to 85 ? c 83940dkilft ics83940dil ?lead-free? 32 lead vfqfn tape & reel -40 ? c to 85 ? c
ics83940dyi revision c may 19, 2016 18 ?2016 integrated device technology, inc. ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer revision history sheet rev table page description of change date a t2 2 7 pin characteristics table - changed r out 25 ? maximum to 28 ? maximum. delete r pullup row. 3.3v output load ac test circuit di agram - corrected gnd equation to read -1.65v... from -1.165v... added lvttl to title. updated format. 12/12/02 a t8 1 9 10 13 features section - added lead-free bullet. application information section - added recommendations for unused input and output pins. application information section - added lvpecl clock input interface. ordering information table - added lead-free part number, marking, and note. updated datasheet format. 11/27/06 a 3 absolute maximum ratings - corr ected storage te mperature from ?-40c to 125c? to ?-65c to 150c?. 2/21/07 b t6b t7b t8 1 13 14 16 17 added 32 lead vfqfn pin assignment. added vfqfn thermal release path section. added 32 vfqfn thermal table. added 32 lead vfqfn package and dimensions table. ordering information table - added 32 lead vfqfn ordering information. converted datasheet format. 8/13/09 c t2 2 11 16 pin characteristics table - r out error, typical spec deleted. updated wiring the differential in put to accept single-ended levels. updated 32 vfqfn package outline. 9/7/10 c t8 17 removed leaded orderables from ordering information table 11/27/12 c 1, 14,16 deleted ?proposed? stamp 3/20/13 c product discontinuation notice - last time buy expires may 6, 2017. (83940dkilf) pdn cq-16-01 5/19/16
ics83940di data sheet low skew, 1-to-18 lvpecl-to-lvcmos/lvttl fanout buffer disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the ri ght to modify the products and/or specif ications described herein at any time and at idt? s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when in stalled in customer products. the informa tion contained herein is provided without re presentation or warranty of any kind, whether expr ess or implied, including, but not limited to, the suitability of idt?s products for any partic ular purpose, an implied warranty of merc hantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt?s products are not intended for use in applications involving extreme environmenta l conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to signifi- cantly affect the health or safety of users. anyone using an id t product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered tr ademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2016. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support sales clocks@idt.com +480-763-2056 we?ve got your timing solution

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